Summary
Mr. Majid Ali completed his BS in Electrical Engineering from Namal University Mianwali. His expertise spans Verilog, SystemVerilog, Python, C/C++ Programming, RISC-V Architecture-based Processor Design and Verification, IoT and Embedded Systems. With a solutions-focused approach, he is committed to translating technical knowledge into real-world applications.
Academic Background
BS Electrical Engineering
(Digital System Design, RISC-V Architecture base Processor Design, IoT, Embedded System )
Namal UNiversity, MIanwali
2024
Conference Publications
Integration and Verification of L1 Data Cache in SweRV EH1 RISC-V Core
23-May-2024
RISC-V, an open-source instruction set architecture, has characteristics of high performance, modularity and easy expansion, therefore, numerous numbers of open-source cores have been employed in academic and commercial projects within a few years. Caches significantly boost CPU performance by storing frequently used data closer to the processor to reduce memory latency. This paper details our contribution to open-source hardware: integrating a parameterized set-associative Level 1 data cache with a Least Recently Used (LRU) replacement policy into the SweRV EH1 core, a widely used 32-bit RISC-V core. Supporting cache with a write-through policy and analysis of the hit/miss rate upon CPU requests. Design verification is done via standard and open-source verification tools.
Courses
- Computer Architecture
- Object Oriented Programming
- Application of Information and Communication Technologies (ICT)
Namal University